| IP명 | CMOS Negative Group Delay Circuit Using Source Series Feedback Circuit and Shunt Resonating Resistance. | ||
|---|---|---|---|
| Category | Analog | Application | NGD |
| 실설계면적 | 1.15㎛ X 0.65㎛ | 공급 전압 | 1.2V |
| IP유형 | Hard IP | 동작속도 | 1.95GHz |
| 검증단계 | Simulation | 참여공정 | DB110-1401 |
| IP개요 | Negative Group Delay Circuit (NGDC) basically in a narrow frequency band NGD has the characteristics, insertion loss (IL) can be seen that a large. To overcome such problems, the NGD circuit with cascade structure was implemented. And in cascade nmos stage of the bias part of the off chip process can reduce the size of the layout. However, too many inductor layout on NGD taken place, so here's NGD bonding wire inductor as well as the off chip design, by more than the basic rf devices can increase the Q factor. And off chip to change the Q factor can be controlled by giving NGD and IL. Insert the shielding function of the inductor layout in the DRC, LVS, LPE process, according to the implementation of the maximum chip size was smaller. pad for bonding wire size is set to 100 × 100um was designed without difficulty to the wire. |
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