| IP개요 |
This work presents a command-aware hybrid LDO(CA-HLDO) designed to reduce voltage droop caused by WDQS buffers in HBM to less than 10 mV, while consuming only 150 μA of quiescent current and using a 20 pF capacitor. Leveraging the unique property of memory, in which circuits operate based on commands from the host, the CA-HLDO supplies optimal current immediately when WDQS toggles, thereby minimizing voltage droop and the resultant PSIJ in the output clock. Also, by utilizing low-frequency power-supply rejection (PSR) of ALDO and highfrequency PSR of DLDO, this LDO will also achieve PSR of less than -10 dB across all frequencies. |
