| IP명 | Pipelined SAR ADC for Power Scalable Mixed-Signal In-Memory Computing Macro in Energy-Efficient DNN Accelerators. | ||
|---|---|---|---|
| Category | Mixed | Application | DNN Accelerators |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.1V |
| IP유형 | Hard IP | 동작속도 | 500MEGHz |
| 검증단계 | Silicon | 참여공정 | SF28-2402 |
| IP개요 | To efficiently provide power to PIM and DNN accelerators, a pipelined SAR ADC has been designed. The ADC utilizes body biasing, which demonstrates outstanding performance in FD-SOI. | ||
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