| IP개요 |
A fully integrated 59 dB dynamic range CMOS receiver front-end with constant output-referred third-order intercept point (OIP3) over gain reduction is designed using a 65-nm CMOS process for IoT applications. For wideband input impedance matching in sub-GHz band, the differential output signal generated from the single-to-differential (S2D) converter is fed back into the input through the differential-to-single (D2S) buffer and feedback resistor. To implement the gain control with near constant output 1 dB compression point (OP1dB) and OIP3, it has two separate gain paths by placing two optimized S2D converters for low noise and high linearity respectively. When a very strong signal is received, the receiver front-end disables the feedback path and attenuates the input signal through pi-attenuator providing near constant impedance. The mixer is a type of highly linear currentcommutating passive mixer. In the simulation, the proposed receiver front-end shows an average conversion gain of 48.8 dB, double-sideband noise figure (NFDSB) of 3.3 dB, and OIP3 of +15.8 dBm at high gain mode over the operating frequency band. In addition, it achieves a gain range of about 59 dB with near constant OIP3. The power dissipation is 12.6 mW from a 1.2 V supply voltage. |
