| IP개요 |
This work presents a D-band PLL using the complementary power-gating injection-locked frequency multiplier phase detector (CPG-ILFM PD) that can generate a low reference spur, and low jitter output signal. By adopting CPG-ILFM PD, it can reduce the reference spur significantly by avoiding binary frequency-shift-keying (BFSK) modulation of the frequency of the MVCO (fOUT). Additionally, it can achieve a low jitter output signal by enabling full period operation of CPG-ILFM PD, while the half period operation of the single power-gating injection locked frequency multiplier phase detector (PG-ILFM PD) limits the increase phase detection gain, KPD. According to the simulation result, the proposed D-Band PLL using the CPG-ILFM PD generated a -51 dBc reference spur and 66 fsrms jitter output signal, it concurrently achieved a high FoMJIT among the state-of-the-art W/D-band PLLs. |
