| IP명 | A Novel Multi-Level Cell Sensing Scheme for Resistive Nonvolatile Memory | ||
|---|---|---|---|
| Category | Analog | Application | Multi level sensing |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V, 1.8VV |
| IP유형 | Hard IP | 동작속도 | 5MHz |
| 검증단계 | Silicon | 참여공정 | SS28-2402 |
| IP개요 | Based on the simulation results, the proposed MLC-SS can achieve read yield comparable to two-step SS with only one reference and less time. By using actual chip, all assumptions made with simulation results can be confirmed. Confirming simulation results is critical for further optimization. | ||
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