| IP개요 |
Pipelined-SAR ADCs have proven its capability of achieving high-speed and high-resolution with excellent energy efficiency. Like a typical pipelined ADC, the main bottleneck with pipelined SAR ADCs is the design of the residue amplifier (RA). By utilizing a dual-residue pipelined SAR ADC structure with single amplifier, the need for accurate gain nor gain matching will be eliminated making the use of open-loop RAs possible. In addition, the embedded buffer using a core supply having a rail-to-rail signal swing that is very desirable for design scaling increases the driving strength of the architecture which also makes the ADC suitable for time-interleaving scheme. Furthermore, the proposed ADC adopts the kT/C noise cancellation technique for CDAC, enabling the use of smaller unit cap while meeting the kT/C noise requirements. With this, a faster CDAC settling is possible which improves the overall speed of the ADC. To further enhance the speed of the single channel, a pseudo-loop unrolling in the 2nd stage is proposed which hides the dynamic amplifier (comparator) clock generation time behind the latching and DAC settling time. Lastly, a reliable timing skew calibration that is applicable to any number of channels to test the functionality of the single-channel is proposed. |
