| IP개요 |
This memory macro is an embedded 2T DRAM organized as 8192-word × 8-bit, which combines the read/write/refresh characteristics of semiconductor RAM with logic-compatible dynamic data storage. The memory cells are composed of a high-threshold write transistor and a standard-threshold read transistor. The bit data are stored on the parasitic capacitances within the cells. Features such as compact bit-cell area, decoupled read/write path and nondestructive read-out make it a potent alternative for embedded memories. The embedded DRAM is designed in a 0.11-?m logic CMOS technology. The memory arrays operate with a 1.2 volt single power supply; SRAM-like I/O interface; /CS-controlled 128-row refresh; and nondestructive read with speed comparable to 6T SRAM but 65 % smaller cell area. This DRAM macro utilizes the JEDEC standard bytewide SRAM pinout. |
