| IP개요 |
Abstract - Recently, long-reach high-speed serial links above 224 Gb/s are being designed with analog-digital-converter (ADC)-based digital-signal-processing (DSP) structures. This study intends to design a 4-level pulse amplitude modulation (PAM-4) transceiver and thoroughly compare the performance and area of receiver (RX) DSPs. Conventional feed-forward-equalizer (FFE) and decisionfeedback-equalizer (DFE) will be designed together to compare their performance, and an equalizer method that can have an area efficient scheme and high bit-error-rate (BER) will be proposed. The proposed PAM-4 transmitter (TX) includes a pseudorandom-binarysequence (PRBS) generator and digital-to-analog converter (DAC), and the PAM-4 RX includes an FFE designed with a distributed arithmetic structure and a loop break DFE to relax feedback loops. Each block will be optimized based on signal-to-noise-ratio (SNR) and BER, considering the relationship between various design parameters. |
