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IP명 Digital Equalizer for High-Speed ADC-Based Serial Links
Category Mixed Application ultra high speed wireline
실설계면적 1㎛ X 2㎛ 공급 전압 0.9V
IP유형 Hard IP 동작속도 500MHz
검증단계 Silicon 참여공정 HM-2402
IP개요 Modern long-reach high-speed serial links for data rate above 112 Gb/s are mostly based on the analog-digital converter (ADC) with extensive equalization in the DSP implemented in the fully digital circuit on the receiver (RX) side. This work intends to thoroughly compare the RX-side DSP equalizers in terms of silicon footprint, power consumption, and achievable speed for various orders of pulse-amplitude modulation (PAM). Despite the same target data rate (e.g., 224 Gb/s), non-return-to-zero (NRZ), PAM-4, and PAM-8 all have different required analog front-end (AFE) and DSP design specifications, and the optimized silicon performances of their DSPs will be a different one from another. In this work, the RX DSP equalizers will be implemented with careful optimization strategy for each of NRZ, PAM-4, and PAM-8, respectively, considering the relationships among multiple design parameters including the required DSP operation frequencies, bit precisions, and level of approximation.
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