| IP개요 |
This IP targets a CMOS Ising solver that can solve combinatorial optimization problems. Unlike previous digital spin circuits that used MAC units for calculating weighted sums, spin circuits in this IP performs the calculation in analog domain by adopting binary-weighted capacitors and a comparator. This reduces the dependence of calculation time and the number of associated interactions. Therefore, the proposed spin circuit is designed to support up to 16 connections between correlated spins. The hybrid structure of spin configuration allows 9 parallel spin updates, so further speedup is expected. Core frequency of the system was 3 GHz in post-layout simulation. Designed wih a CMOS 28-nm technology, more than a thousand spins are integrated in a single die. |
