| IP개요 |
The system integrates an analog power control, a digital control, an ADC, and memory in a single chip. To meet flexible power requirement, rectifier and limiter are realized off-chip. The analog power control block includes a bandgap, fixed-output LDO regulators (1.8 and 3.3 V), an adaptive LDO regulator, and a battery charge controller. The battery charge controller provides three reference current for TC, CC, and CV modes. The actual charging current is continuously compared with the reference. Using the result, the charge controller generates the feedback voltage VFB for the adaptive LDO regulator. The adaptive LDO regulator receives an input VLIMIT from a limiter, and generates the supply voltage VADAP for the power transistor MP0. The VADAP closely follows the battery voltage VBAT for a high efficiency. The digital control block is implemented based on Qi standard. The memory stores charging status and information needed to communicate with a power transmitter. An 8-bit ADC is used for battery level monitoring and BRC function. |
