| IP개요 |
In this paper, we propose a convolution-based feature extractor (CoFEx) equipped with an improved systolic array (SA) architecture. In the proposed CoFEx, the SA architecture for performing convolution operations consists of three stages: pre-operation stage, operation stage, and post-operation stage. The pre-operation stage is the step where all feature map data are aligned in the processing elements (PE) within the SA structure before performing the convolution operation. After passing through the pre-operation stage, which requires a short time of 3 clocks based on a 3x3 kernel size, there is the operation stage where the actual convolution operation is performed. In the operation stage, convolution operations are performed more quickly compared to the conventional SA architecture by reusing feature map data. The post-operation stage is the phase where the convolution operation results are outputted, continuously providing the results for the columns of the input feature map. The proposed architecture performs floating-point operations following the IEEE 754 standard, enhancing the accuracy of computations, and provides functionalities such as padding, pooling, and activation functions. We designed the proposed architecture with Verilog HDL and verified by simulation. The designed architecture was implemented on field programmable gate array (FPGA). We will fabricate the CoFEx with Samsung 28nm RFCMOS 1-poly 10LM technology. The designed processor operates in 1.2V, 50MHz frequency and the circuit is digital type. |
