| IP개요 |
– This work addresses two core circuits. One is a LDO with low input voltage and high efficiency. and another is sub-1-V operatable Bandgap Reference Circuit for LDO. For proposed LDO, it consists of an NMOS pass transistor with switched -capacitor charge pump(SCCP) for lowering dropout voltage(VDO). Also, it regulates output voltage in an analog way with low supply input voltage(VIN). By doing so, the proposed LDO has better regulation accuracy and less power loss than digital LDO. As a result, it can increase battery lifetime and is suitable for low-power PIM applications. For proposed BGR, it consists of 2-stage OP-amp for high loop gain to achieve supply voltage variation robustness and suitable PSRR at 1MHz. Also, it operates at sub-1-V voltage(VDD) using diode forward voltage with voltage dividing resistors. By doing so, the proposed BGR provides LDO a reference voltage robust to PVT variation and power noise at high frequency with low supply voltage. This LDO and BGR circuit will be fabricated in Samsung 28nm CMOS process. |
